1. Field of the Invention
The present invention relates to a high performance thin film transistor having an SOI structure and a manufacturing method therefor.
2. Related Background Art
Recently, a thin film transistor has been attracting attention as an element which constitutes a three-dimensional integrated circuit, a contact sensor or a plane display device. In particular, a study has been made in order to improve the performance of a silicon thin film transistor by approximating its crystallinity to that of the monocrystal substance. Another study has been made in order to significantly improve the mobility by utilizing the specific mechanism in such a manner that the thickness of the thin film is considerably reduced (0.1 .mu.m or less). However, although each specific characteristic has attracted attention according to the above-described studies, the relative changes between the other transistor characteristics have not been sufficiently detected.
The inventor of the present invention has studied the overall electrical characteristics of the thin film transistor having the SOI structure, resulting in a knowledge to be found from simulations that, if the thickness of the semiconductor layer becomes thinner than a predetermined thickness, the drain voltage resistance at the time when the gate voltage is 0V (when it is turned off) rapidly deteriorates in comparison to that displayed by a thick film semiconductor layer. Another fact was found from simulations that, although the avalanche breakdown, which determines the drain voltage resistance and which takes place at the drain end, arises in the vicinity of the gate interface in the case of a thick semiconductor, the same arises in the vicinity of an interface with the base insulating substrate in the case where the thickness is smaller than the predetermined thickness.
More particularly, the conventional simulation made about an SOI-type MIS-FET, which was constituted by forming, on a thick insulating substrate, a thin film semiconductor layer, a gate insulating film and a gate electrode, found a fact that the maximum electric fields were concentrated in a vicinity of the gate interface and the avalanche breakdown was first taken place in the vicinity of the gate interface in such a manner that the above-described tendency was maintained regardless of the thickness of the semiconductor layer.
The inventor has made simulations while taking into consideration the fixed charge (Qss) at the interface between the base insulating substrate and the semiconductor layer which was considered to be present in an actual SOI structure. As a result, a fact was found that, although the electric field was strong on the gate interface side in comparison to that at the portion adjacent to the base interface, the avalanche breakdown actually took place in the vicinity of the base interface. Although the detailed mechanism is being researched now, it can be considered that the avalanche breakdown depends upon not only the electric field but also the number of carriers and thereby the number of the carriers is further affected at the base interface while an assumption is made that the equivalent Qss is applied to the gate and the portion adjacent to the base interface.